The present invention relates to a technology effectively applicable to cell periphery layout techniques or breakdown voltage enhancement techniques in semiconductor devices (or semiconductor integrated circuit devices), especially, power semiconductor devices such as power MOSFETs.
Japanese Unexamined Patent Publication No. 2008-124346 (Patent Document 1) or U.S. Pat. No. 7,642,597 (Patent Document 2) discloses an example of the following power MOSFET (Metal Oxide Semiconductor Field Effect Transistor): a power MOSFET manufactured using a multi-epitaxy technique or an epitaxy trench filling technique and having a so-called semi-super junction structure in which a super junction structure is introduced up to some midpoint in a drift region. In this example, such an impurity profile that the impurity concentration is gradually reduced from top to bottom is formed in a p-type column region comprising a semi-super junction structure. Electric field concentration at the lower end portion of a trench field plate is thereby reduced to achieve a high-breakdown voltage characteristic and low on resistance.
Japanese Unexamined Patent Publication No. 2004-119611 (Patent Document 3) discloses an example of a power MOSFET having a semi-super junction structure manufactured mainly using a multi-epitaxy technique. In this example, such an impurity profile that the impurity concentration is gradually increased from top to bottom is formed in an n-type column region comprising a semi-super junction structure. Degradation in breakdown voltage due to charge unbalance between an n-type column region and a p-type column region is thereby reduced.
Japanese Unexamined Patent Publication No. 2008-258442 (Patent Document 4) or US Patent Publication No. 2008-246079 (Patent Document 5) discloses an example of a power MOSFET having a semi-super junction structure manufactured mainly using a multi-epitaxy technique. In this example, an impurity profile high at the central part is formed in an n-type column region and a p-type column region comprising a semi-super junction structure. Depletion at the upper and lower ends is thereby facilitated to reduce electric field concentration at these parts.
Japanese Unexamined Patent Publication No. 2008-91450 (Patent Document 6) or US Patent Publication No. 2008-237774 (Patent Document 7) discloses an example of a power MOSFET having a semi-super junction structure manufactured mainly using a multi-epitaxy technique. In this example, such an impurity profile that the impurity concentration is reduced stepwise from top to bottom is formed in an n-type column region and a p-type column region comprising a semi-super junction structure to achieve a high-breakdown voltage characteristic and low on resistance.
Japanese Unexamined Patent Publication No. 2007-300034 (Patent Document 8) or US Patent Publication No. 2008-17897 (Patent Document 9) discloses an example of a power MOSFET having a semi-super junction structure manufactured mainly using an epitaxy trench filling technique. In this example, the width of an n-type column region and a p-type column region comprising a semi-super junction structure is made different between top and bottom. (Specifically, the width of the lower part of the p-type column region is reduced.) Diffusion of boron at the lower part of a column is thereby suppressed to prevent increase in on resistance.
Japanese Unexamined Patent Publication No. 2006-66421 (Patent Document 10) or U.S. Pat. No. 7,420,245 (Patent Document 11) discloses an example of the following power MOSFET manufactured using a multi-epitaxy technique: a power MOSFET having a so-called full-super junction structure (or simply referred to as “super junction structure”) in which a super junction structure is introduced so that it penetrates a drift region. In this example, an n-type column region and a p-type column region comprising a super junction structure are each divided into two sections, an upper section and a lower section. The concentration of the upper section is increased to reduce degradation in breakdown voltage due to charge unbalance between the n-type column region and the p-type column region.